1 ? caution: these devices are sensitive to electrosta tic discharge; follow proper ic handling procedures. 1-888-intersil or 321-724-7143 | intersil (and design) is a registered trademark of intersil americas inc. copyright ? intersil americas inc. 2003. all rights reserved all other trademarks mentioned are the property of their respective owners. cmos video speed, 8- bit, 50 msps, r2r d/a converters the ca3338 family are cmos/sos high speed r2r voltage output digital-to-analog converte rs. they can operate from a single +5v supply, at video speeds, and can produce ?rail-to-rail? output swings. internal level shifters and a pin for an optional second supply provide for an output range below digital ground. the data comp lement control allows the inversion of input data whil e the latch enable control provides either feedthrough or latched operation. both ends of the r2r ladder network are available externally and may be modulated for gain or offset adjustments. in addition, ?glitch? energy has been kept very low by segmenting and thermometer encoding of the upper 3 bits. the ca3338 is manufactured on a sapphire substrate to give low dynamic power dissipa tion, low output capacitance, and inherent latch-up resistance. ordering information features ? cmos/sos low power ? r2r output, segmented for low ?glitch? ? cmos/ttl compatible inputs ? fast settling: (typ) to 1 / 2 lsb . . . . . . . . . . . . . . . . . . 20ns ? feedthrough latch for clocked or unclocked use ? accuracy (typ) . . . . . . . . . . . . . . . . . . . . . . . . . . 0.5 lsb ? data complement control ? high update rate (typ) . . . . . . . . . . . . . . . . . . . . . 50mhz ? unipolar or bipolar operation applications ? tv/video display ? high speed oscilloscope display ? digital waveform generator ? direct digital synthesis pinout ca3338, CA3338A (pdip, soic) top view part number linearity (inl, dnl) temp. range ( o c) package pkg. no. ca3338e 1.0 lsb -40 to 85 16 ld pdip e16.3 CA3338Ae 0.75 lsb -40 to 85 16 ld pdip e16.3 ca3338m 1.0 lsb -40 to 85 16 ld soic m16.3 CA3338Am 0.75 lsb -40 to 85 16 ld soic m16.3 14 15 16 9 13 12 11 10 1 2 3 4 5 7 6 8 d7 d6 d5 d4 d3 d2 v ss d1 v dd comp v ref + v out v ref - v ee d0 le fn1850.3 ca3338, CA3338A data sheet may 2003
2 functional diagram comp to 7-line v dd d7 d6 d5 d4 d3 d2 d1 d0 v ss 16 15 14 1 2 3 4 5 6 7 9 8 thermometer encoder 3-bit level shifters feedthrough latches 8r 4r 2r 2r 2r 2r 2r 2r 8r 8r 8r 4r 13 10 v ee v ref - v out v ref + 12 11 2r r r r le r ? 160 ? r r r r ca3338, CA3338A ca3338, CA3338A
3 ca3338, CA3338A absolute maximum rati ngs thermal information dc supply-voltage range. . . . . . . . . . . . . . . . . . . . . . . -0.5v to +8v (v dd - v ss or v dd - v ee , whichever is greater) input voltage range digital inputs (le, comp d0 - d7). . . . v ss - 0.5v to v dd + 0.5v analog pins (v ref +, v ref -, v out ) . . . .v dd - 8v to v dd + 0.5v dc input current digital inputs (le, comp, d0 - d7) . . . . . . . . . . . . . . . . . . 20ma recommended supply voltage range . . . . . . . . . . . . . 4.5v to 7.5v operating conditions temperature range (t a ) plastic package, e suffix, m suffix . . . . . . . . . . . . . . -40 o c to 85 o c thermal resistance (typical, note 1) ja ( o c/w) jc ( o c/w) pdip package . . . . . . . . . . . . . . . . . . . 90 n/a soic package . . . . . . . . . . . . . . . . . . . 100 n/a maximum junction temperature plastic packages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .150 o c maximum storage temperature range, t stg . . . . -65 o c to 150 o c maximum lead temperature (soldering 10s) . . . . . . . . . . . . .300 o c (soic - lead tips only) caution: stresses above those listed in ?abs olute maximum ratings? may cause permanent dam age to the device. this is a stress o nly rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. note: 1. ja is measured with the component mount ed on an evaluation pc board in free air. electrical specifications t a = 25 o c, v dd = 5v, v ref + = 4.608v, v ss = v ee = v ref - = gnd, le clocked at 20mhz, r l 1 m ? , unless otherwise specified parameter test conditions min typ max units accuracy resolution 8 - - bits integral linearity error see figure 4 ca3338 - - 1lsb CA3338A - - 0.75 lsb differential linearity error see figure 4 ca3338 - - 0.75 lsb CA3338A - - 0.5 lsb gain error input code = ff hex , see figure 3 ca3338 - - 0.75 lsb CA3338A - - 0.5 lsb offset error input code = 00 hex ; see figure 3 - - 0.25 lsb digital input timing update rate to maintain 1 / 2 lsb settling dc 50 - mhz update rate v ref - = v ee = -2.5v, v ref + = +2.5v dc 20 - mhz set up time t su1 for low glitch - -2 - ns set up time t su2 for data store - 8 - ns hold time t h for data store - 5 - ns latch pulse width t w for data store - 5 - ns latch pulse width t w v ref - = v ee = -2.5v, v ref + = +2.5v - 25 - ns output parameters r l adjusted for 1v p-p output output delay t d1 from le edge - 25 - ns output delay t d2 from data changing - 22 - ns rise time t r 10% to 90% of output - 4 - ns settling time t s 10% to settling to 1 / 2 lsb - 20 - ns output impedance v ref + = 6v, v dd = 6v 120 160 200 ? glitch area - 150 - pv/s glitch area v ref - = v ee = -2.5v,v ref + = +2.5v - 250 - pv/s
4 ca3338, CA3338A reference voltage v ref + range (+) full scale, note 2 v ref - + 3 - v dd v v ref - range (-) full scale, note 2 v ee -v ref + - 3 v v ref + input current v ref + = 6v, v dd = 6v - 40 50 ma supply voltage static i dd or i ee le = low, d0 - d7 = high - 100 220 a le = low, d0 - d7 = low - - 100 a dynamic i dd or i ee v out = 10mhz, 0v to 5v square wave - 20 - ma dynamic i dd or i ee v out = 10mhz, 2.5v square wave - 25 - ma v dd rejection 50khz sine wave applied - 3 - mv/v v ee rejection 50khz sine wave applied - 1 - mv/v digital inputs d0 - d7, le, comp high level input voltage note 2 2 - - v low level input voltage note 2 - - 0.8 v leakage current - 1 5 a capacitance - 5 - pf temperature coefficients output impedance - 200 - ppm/ o c note: 2. parameter not tested. but guaranteed by design or characterization. electrical specifications t a = 25 o c, v dd = 5v, v ref + = 4.608v, v ss = v ee = v ref - = gnd, le clocked at 20mhz, r l 1 m ? , unless otherwise specified (continued) parameter test conditions min typ max units
5 ca3338, CA3338A digital signal path the digital inputs (le, comp, and d0 - d7) are of ttl compatible hct high speed cmos design: the loading is essentially capacitive and the logic threshold is typically 1.5v. the 8 data bits, d0 (weighted 2 0 ) through d7 (weighted 2 7 ), are applied to exclusive or gates (see functional diagram). the comp (data complement) control provides the second input to the gates: if comp is high, the data bits will be inverted as they pass through. the input data and the le (latch enable) signals are next applied to a level shifter. the inputs, operating between the levels of v dd and v ss , are shifted to operate between v dd and v ee . v ee optionally at ground or at a negative voltage, will be discussed under bipolar operation. all further logic elements except the output drivers operate from the v dd and v ee supplies. the upper 3 bits of data, d5 through d7, are input to a 3-to-7 line bar graph encoder. the encoder outputs and d0 through d4 are applied to a feedthrough latch, which is controlled by le (latch enable). latch operation data is fed from input to output while le is low: le should be tied low for non-clocked operation. non-clocked operation or changi ng data while le is low is not recommended for applications requiring low output ?glitch? energy: there is no guarantee of the simultaneous changing of input data or the equal propagation delay of all bits through the converter. several parameters are given if the converter is to be used in either of these modes: t d2 gives the delay from the input changing to the output changing (10%), while t su2 and t h give the set up and hold times (referred to le rising edge) needed to latch data. see figures 1 and 2. clocked operation is needed for low ?glitch? energy use. data must meet the given t su1 set up time to the le falling edge, and the t h hold time from the le rising edge. the delay to the output changing, t d1 , is now referred to the le falling edge. there is no need for a square wave le clock; le must only meet the minimum t w pulse width for successful latch operation. generally, output timing (desired accuracy of settling) sets the upper limit of usable clock frequency. output structure the latches feed data to a row of high current cmos drivers, which in turn feed a modified r2r ladder network. the ?n? channel (pull down) transistor of each driver plus the bottom ?2r? resistor are returned to v ref - this is the (-) full- scale reference. the ?p? channel (pull up) transistor of each driver is returned to v ref +, the (+) full-scale reference. in unipolar operation, v ref - would typically be returned to analog ground, but may be raised above ground (see specifications). there is s ubstantial code dependent current that flows from v ref + to v ref - (see v ref + input current in specifications), so v ref - should have a low impedance path to ground. pin descriptions pin name description 1 d7 most significant bit 2 d6 input 3d5 data 4d4 bits 5 d3 (high = true) 6d2 7d1 8v ss digital ground 9d 0 least significant bit. input data bit 10 v ee analog ground 11 v ref - reference voltage negative input 12 v out analog output 13 v ref + reference voltage positive input 14 comp data complement control input. active high 15 le latch enable input. active low 16 v dd digital power supply, +5v input data latch t su1 t su2 t w t h enable latched latched data feedthrough figure 1. data to latch enable timing t d1 t d2 t r t s 1 / 2 lsb 1 / 2 lsb 90% 10% input latch enable output voltage data figure 2. data and latch enable to output timing
6 ca3338, CA3338A in bipolar operation, v ref - would be returned to a negative voltage (the maximum vo ltage rating to v dd must be observed). v ee , which supplies the gate potential for the output drivers, must be returned to a point at least as negative as v ref -. note that the maximum clocking speed decreases when the bipolar mode is used. static characteristics the ideal 8-bit d/a would have an output equal to v ref - with an input code of 00 hex (zero scale output), and an output equal to 255/256 of v ref + (referred to v ref -) with an input code of ff hex (full scale output). the difference between the ideal and actual values of these two parameters are the offset and gain errors, respectively; see figure 3. if the code into an 8-bit d/a is changed by 1 count, the output should change by 1/255 (full scale output - zero scale output). a deviation from this step size is a differential linearity error, see figure 4. note that the error is expressed in fractions of the ideal step size (usually called an lsb). also note that if the (-) differential linearity error is less (in absolute numbers) than 1 lsb, the device is monotonic. (the output will always increase for increasing code or decrease for decreasing code). if the code into an 8-bit d/a is at any value, say ?n?, the output voltage should be n/255 of the full scale output (referred to the zero scale output). any deviation fr om that output is an integral linearity error, usually expressed in lsbs. see figure 4. note that offset and gain errors do not affect integral linearity, as the linearity is referenced to actual zero and full scale outputs, not ideal. absolute accuracy would have to also take these errors into account. dynamic characteristics keeping the full-scale range (v ref + - v ref -) as high as possible gives the best linearity and lowest ?glitch? energy (referred to 1v). this provides the best ?p? and ?n? channel gate drives (hence saturation resistance) and propagation delays. the v ref + (and v ref - if bipolar) terminal should be well bypassed as near the chip as possible. ?glitch? energy is defined as a s purious voltage that occurs as the output is changed from one voltage to another. in a binary input converter, it is usually highest at the most significant bit transition (7f hex to 80 hex for an 8 bit device), and can be measured by displaying the output as the input code alternates around that point. the ?glitch? energy is the area between the actual output display and an ideal one lsb step voltage (subtracting negative area from positive), at either the positive or negative-going step. it is usually expressed in pv/s. the ca3338 uses a modified r2r ladder, where the 3 most significant bits drive a bar graph decoder and 7 equally weighted resistors. this makes the ?glitch? energy at each 1 / 8 scale transition (1f hex to 20 hex , 3f hex to 40 hex , etc.) essentially equal, and far less than the msb transition would otherwise display. for the purpose of comparison to other converters, the output should be resistively divided to 1v full scale. figure 5 shows a typical hook-up for checking ?glitch? energy or settling time. the settling time of the a/d is mainly a function of the output resistance (approximately 160 ? in parallel with the load resistance) and the load plus internal chip capacitance. both ?glitch? energy and settling ti me measurements require very good circuit and probe grounding: a probe tip connector such as tektronix part number 131-0258-00 is recommended. 255/256 254/256 253/256 3/256 2/256 1/256 0 00 01 02 03 fd fe ff = ideal transfer curve = actual transfer curve offset error (shown +) output voltage as a fraction of v ref + - v ref - gain error (shown -) input code in hexadecimal (comp = low) figure 3. d/a offset and gain error 0 00 output voltage c b from ?0? scale integral linearity error (shown -) straight line to full scale voltage input code = ideal transfer curve = actual transfer curve a = ideal step size (1/255 of full b - a = +differentia l linearity error c - a = -differential linearity error a scale -?0? scale voltage) figure 4. d/a integral and differential linearity error
7 clock 8 data bits +5v 15 16 14 8 1-7, 9 le d0 - d7 v dd comp v ss ca3338 v out v ref + v ee 12 13 11 10 +5v +2.5v -2.5v r1 r2 probe tip remote v out r3 v ref - or bnc connector digital ground analog ground + + + figure 5. ca3338 dynamic test circuit function connector r1 r2 r3 v out (p-p) oscilloscope display probe tip 82 ? 62 ? n/c 1v match 93 ? cable bnc 75 160 93 1v match 75 ? cable bnc 18 130 75 1v match 50 ? cable bnc short 75 50 0 79v notes: 3. v out(p-p) is approximate, and will vary as r out of d/a varies. 4. all drawn capacitors are 0.1 f multilayer ceramic/4.7 f tantalum. 5. dashed connections are for unipolar operation. solid connection are for bipolar operation. notes: 1. both v ref + pin and 392 ? resistor should be bypassed within 1 / 4 inch. 2. keep nodal capacitance at ca3450 pin 3 as low as possible. 3. v out range = 3v at ca3450. clock 8 data +5v 15 16 14 8 1-7, 9 le d0 - d7 v dd comp v ss ca3338 v out v ref + v ee 12 13 11 10 r v ref - r 11 up to 5 output lines for r = 75 ? , 3 lines for r = 50 ? v out 1 v out n +3.00v at 25ma 4.7 f tan 4.7 f tan 4.7 f tan 4.7 f tan 0.1 f cer. 0.1 f cer. 0.1 f cer. 0.1 f cer. 14 +6v -6v 392 ? 392 ? 1% 10k ? 1k ? 3 4, 5, 12, 13 r r + + + + v out = 1.5v peak 6 7, 8 9 + - ca3450 adjust offset 5pf bits 1% figure 6. ca3338 and ca3450 for driving multiple coaxial lines ca3338, CA3338A
8 ca3338, CA3338A applications the output of the ca3338 can be resistively divided to match a doubly terminated 50 ? or 75 ? line, although peak-to-peak swings of less than 1v may result. the output magnitude will also vary with the converte r?s output impedance. figure 5 shows such an application. note that because of the hct input structure, the ca3338 could be operated up to +7.5v v dd and v ref + supplies and still accept 0v to 5v cmos input voltages. if larger voltage swings or better accuracy is desired, a high speed output buffer, such as the ha-5033, ha-2542, or ca3450, can be employed. figure 6 shows a typical application, with the output capable of driving 2v into multiple 50 ? terminated lines. operating and hand ling considerations handling all inputs and outputs of cmos devices have a network for electrostatic protection during handling. recommended handling practices for cmos devices are described in an6525. ?guide to better handling and operation of cmos integrated circuits.? operating operating voltage during operation near the maximum supply voltage limit, care should be taken to avoid or suppress power supply turn-on and turn-off transients, power supply ripple, or ground noise; any of these c onditions must not cause the absolute maximum ratings to be exceeded. input signals to prevent damage to the input protection circuit, input signals should never be greater than v dd nor less than v ss . input currents must not exceed 20ma even when the power supply is off. unused inputs a connection must be provided at every input terminal. all unused input terminals must be connected to either v cc or gnd, whichever is appropriate. table 1. output voltage vs input code and v ref v ref + v ref - step size 5.12v 0 0.0200v 5.00v 0 0.0195v 4.608v 0 0.0180v 2.56v -2.56v 0.0200v 2.50v -2.50v 0.0195v input code 11111111 2 =ff hex 11111110 2 =fe hex 5.1000v 5.0800 4.9805v 4.9610 4.5900v 4.5720 2.5400v 2.5200 2.4805v 2.4610 ? ? ? 10000001 2 =81 hex 10000000 2 =80 hex 01111111 2 =7f hex 2.5800 2.5600 2.5400 2.5195 2.5000 2.4805 2.3220 2.3040 2.2860 0.0200 0.0000 - 0.0200 0.0195 0.0000 -0.0195 ? ? ? 00000001 2 =01 hex 00000000 2 =00 hex 0.0200 0.0000 0.0195 0.0000 0.0180 0.0000 -2.5400 -2.5600 -2.4805 -2.5000
9 ca3338, CA3338A dual-in-line plastic packages (pdip) notes: 1. controlling dimensions: inch. in case of conflict between english and metric dimensions, the in ch dimensions control. 2. dimensioning and tolerancing per ansi y14.5m - 1982. 3. symbols are defined in the ?mo series symbol list? in section 2.2 of publication no. 95. 4. dimensions a, a1 and l are measured with the package seated in je- dec seating plane gauge gs - 3. 5. d, d1, and e1 dimensions do not include mold flash or protrusions. mold flash or protrusions shal l not exceed 0.010 inch (0.25mm). 6. e and are measured with the leads constrained to be perpendic- ular to datum . 7. e b and e c are measured at the lead tips with the leads unconstrained. e c must be zero or greater. 8. b1 maximum dimensions do not include dambar protrusions. dambar protrusions shall not exceed 0.010 inch (0.25mm). 9. n is the maximum number of terminal positions. 10. corner leads (1, n, n/2 and n/2 + 1) for e8.3, e16.3, e18.3, e28.3, e42.6 will have a b1 dimension of 0.030 - 0.045 inch (0.76 - 1.14mm). e a -c- c l e e a c e b e c -b- e1 index 12 3 n/2 n area seating base plane plane -c- d1 b1 b e d d1 a a2 l a1 -a- 0.010 (0.25) c a m bs e16.3 (jedec ms-001-bb issue d) 16 lead dual-in-line plastic package symbol inches millimeters notes min max min max a - 0.210 - 5.33 4 a1 0.015 - 0.39 - 4 a2 0.115 0.195 2.93 4.95 - b 0.014 0.022 0.356 0.558 - b1 0.045 0.070 1.15 1.77 8, 10 c 0.008 0.014 0.204 0.355 - d 0.735 0.775 18.66 19.68 5 d1 0.005 - 0.13 - 5 e 0.300 0.325 7.62 8.25 6 e1 0.240 0.280 6.10 7.11 5 e 0.100 bsc 2.54 bsc - e a 0.300 bsc 7.62 bsc 6 e b - 0.430 - 10.92 7 l 0.115 0.150 2.93 3.81 4 n16 169 rev. 0 12/93
10 all intersil u.s. products are manufactured, asse mbled and tested utilizing iso9000 quality systems. intersil corporation?s quality ce rtifications can be viewed at www.intersil.com/design/quality intersil products are sold by description only. intersil corporation reserves the right to make changes in circuit design, soft ware and/or specifications at any time without notice. accordingly, the reader is cautioned to verify that da ta sheets are current before placing orders. information furnishe d by intersil is believed to be accurate and reliable. however, no responsibility is assumed by intersil or its subsidiaries for its use; nor for any infringements of paten ts or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of intersil or its subsidiari es. for information regarding intersil corporation and its products, see www.intersil.com ca3338, CA3338A small outline plast ic packages (soic) notes: 1. symbols are defined in the ?mo series symbol list? in section 2.2 of publication number 95. 2. dimensioning and tolerancing per ansi y14.5m - 1982. 3. dimension ?d? does not include mold flash, protrusions or gate burrs. mold flash, protrusion and gate burrs shall not exceed 0.15mm (0.006 inch) per side. 4. dimension ?e? does not include inte rlead flash or protrusions. interlead flash and protrusions shall not exceed 0.25mm (0.010 inch) per side. 5. the chamfer on the body is optional. if it is not present, a visual index feature must be located within the crosshatched area. 6. ?l? is the length of terminal for soldering to a substrate. 7. ?n? is the number of terminal positions. 8. terminal numbers are shown for reference only. 9. the lead width ?b?, as measured 0.36mm (0.014 inch) or greater above the seating plane, shall not exceed a maximum value of 0.61mm (0.024 inch) 10. controlling dimension: millimeter. converted inch dimensions are not necessarily exact. index area e d n 123 -b- 0.25(0.010) c a m bs e -a- l b m -c- a1 a seating plane 0.10(0.004) h x 45 o c h 0.25(0.010) b m m m16.3 (jedec ms-013-aa issue c) 16 lead wide body small outline plastic package symbol inches millimeters notes min max min max a 0.0926 0.1043 2.35 2.65 - a1 0.0040 0.0118 0.10 0.30 - b 0.013 0.0200 0.33 0.51 9 c 0.0091 0.0125 0.23 0.32 - d 0.3977 0.4133 10.10 10.50 3 e 0.2914 0.2992 7.40 7.60 4 e 0.050 bsc 1.27 bsc - h 0.394 0.419 10.00 10.65 - h 0.010 0.029 0.25 0.75 5 l 0.016 0.050 0.40 1.27 6 n16 167 0 o 8 o 0 o 8 o - rev. 0 12/93
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